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| MM74C906 Hex Open Drain N-Channel Buffers October 1987 Revised January 2004 MM74C906 Hex Open Drain N-Channel Buffers General Description The MM74C906 buffer employs monolithic CMOS technology in achieving open drain outputs. The MM74C906 consists of six inverters driving six N-channel devices. The open drain feature of these buffers makes level shifting or wire AND and wire OR functions by just the addition of pullup or pull-down resistors. All inputs are protected from static discharge by diode clamps to VCC and to ground. Features s Wide supply voltage range: 3V to 15V s Guaranteed noise margin: 1V s High noise immunity: 0.45 VCC (typ.) s High current sourcing and sinking open drain outputs Ordering Code: Order Number MM74C906M (Note 1) MM74C906N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Logic Diagram Top View (c) 2004 Fairchild Semiconductor Corporation DS005911 www.fairchildsemi.com MM74C906 Absolute Maximum Ratings(Note 2) Voltage at Any Input Pin Voltage at Any Output Pin Operating Temperature Range Storage Temperature Range Power Dissipation Dual-In-Line Small Outline Operating VCC Range Absolute Maximum VCC Lead Temperature (TL) (Soldering, 10 seconds) 260C 700 mW 500 mW 3V to 15V 18V Note 2: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. -0.3V to VCC +0.3V -40C to +85C -65C to +150C DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions CMOS TO CMOS VIN(1) VIN(0) IIN(1) IIN(0) ICC Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Input Current Logical "0" Input Current Supply Current Output Leakage VCC = 4.75V, VIN = VCC - 1.5V VCC = 4.75V, VOUT = 18V CMOS/LPTTL INTERFACE VIN(1) VIN(0) Logical "1" Input Voltage Logical "0" Input Voltage VCC = 4.75V VCC = 4.75V VCC = 4.75V, VIN = 1V + 0.1 VCC VCC = 4.75V, VOUT = 0.5V VCC = 4.75V, VOUT = 1.0V VCC = 10V, VIN = 2V VCC = 10V, VOUT = 0.5V VCC = 10V, VOUT = 1V 4.2 8.4 20 30 mA mA 2.1 4.2 8.0 12.0 mA mA VCC - 1.5V 0.8 V V 0.005 5 A VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V, Output Open -1.0 0.005 -0.005 0.05 15 3.5 8.0 1.5 2 1 V V V V A A A Min Typ Max Units OUTPUT DRIVE CURRENT www.fairchildsemi.com 2 MM74C906 AC Electrical Characteristics TA = 25C, CL = 50 pF, unless otherwise specified Symbol tpd Parameter Propagation Delay Time to a Logical "0" (Note 3) Conditions Min Typ Max Units VCC = 5.0V, R = 10k VCC =10V, R = 10k tpd Propagation Delay Time to a Logical "1" VCC = 5.0V (Note 4) VCC = 10V (Note 4) CIN COUT CPD Input Capacitance Output Capacity Power Dissipation Capacity (Note 5) (Note 5) (Note 6) Per Buffer 5.0 20 30 150 75 ns ns 150 + 0.7 RC 75 + 0.7 RC ns ns pF pF pF Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: "C" used in calculating propagation includes output load capacity (CL) plus device output capacity (COUT). Note 5: Capacitance is guaranteed by periodic testing. Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note, AN-90. (Assumes outputs are open). Typical Applications Wire AND Gate Note: Can be extended to more than 2 inputs. CMOS or TTL to CMOS at a Higher VCC 3 www.fairchildsemi.com MM74C906 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 MM74C906 Hex Open Drain N-Channel Buffers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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